Pulse interpreter



y 1959' E. P. HAN IiLTON 2,887,676

PULSE LQINTERPRETER- Original Filed Sept. 27. 1954 8 Sheets-Sheet l IN VEN TOR. [aye/7e r? flaw/fan. BY

ATTOENE) May 19, 1959 E. P. HAMILTON 2,887,676

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May 19, 1959' E. P. HAMILTON PULSE iNTERPRETER- 8 Sheets-Sheet 5Original Filed Sept. 27. 1954 lAillI-IIIIII'I INVENTOR; E21 e/FeHam/fan.

ATTORNEY May 19, 1959 E. P. HAMILTON 2,887,676

' PULSE INTERPRETER Original Filed Sept. 27. 1954 8 Sheets-Sheet aMemory M0 Clock 50/0) 20 U063) Pu/5e FLE EE F1E E7 INVENTOR.

3 May 19, 1959 E- P. HAMILTON PULSE INTERPRETER 8 Sheets-Sheet 8Original Filed Sept. 27. 1954 INVENTOR.

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Unified SW65 wnr o PULSE INTERPRETER Eugene P. Hamilton, Richmond,Calif., assignor 'to Marchant Research, Inc., a corporation ofCalifornia Original application September 27, 1954, Serial No. 458,473.Divided and this application May 9, 1956, Serial No. 583,847

8 Claims. (Cl. 340-474) This, invention, which is a division ofapplication Serial No. 458,473, filed September 27, 1954, by George B.Greene et al., relates to computers, and more particularly concerns apulse interpreter in an electronic computer. I

In computers which store large quantitiesof information, for example ina magnetic drum or tape memory, certain modes of data storage give riseto problems in interpreting signals that are produced when stored infermation is read out of the memory unit.

The present invention is illustrated in the environment of a digitalcomputer which employs a magnetic drum memory on which information isstored in the well-known non-restore-to-zero mode as binary s and 1srepresentations, described in detail hereinafter. The patterns of 0s andls stored in this memory is purely a function of the informationrepresented thereby, and the nonrestore-to-zero mode of storage, incombination with a random 0s and 1s distribution, produces a series ofran'-' dom dwells in one or another magnetized state on the For reasonsdescribed hereinafter, such an arrangement often leads to readoutsignals that are nonuniform in amplitude and width. These signalsmustbeaccurately identified with respect to time position in order to assignthem their proper ordinal significance.

It is therefore a primary object of the present invention to provide animproved circuit for interpreting signals that are derived from amagnetic memory having values,

recorded thereon in random order.

It is another object of the invention to interpret sig-.

nals, representing randomly time-spaced value changes, by detecting theproperties of each signal at a plurality of times during the signal, andrelating the; signal to an appropriate one of several predetermined timeintervals in response to such detection.

Other objects of the invention will appear from the fol ice ' Fig. 12 isa block diagram representing the cathodefollower gate of Fig. 11;

gate;

' Fig. 14 is a block diagram representing the pentode gate of Fig. 13;

lowing description, reference being made tothe' accompanying drawings,in which:

Fig. 1 is a schematic diagram of a typical trio'de amplifier;

ode amplifier shown in Fig. 1;

Fig. 3 is a schematic diagram of a typical phase inverter;

Fig. 4 is a block diagram representing the phase in verter of Fig. 3

Fig. 5 is a schematic diagram of a typical cathode follower;

Fig. 6 is a block diagram representing the cathode follower of Fig. 5; IFig. 7 is a schematic diagram of a typical diode gate; Fig. 8 is a blockdiagram representing the diodegate of Fig. 7; i

Fig. 9 is a schematic diagram of atypical triode gate; Fig. 10 is ablock diagram representingthe triode gate of Fig. 9;

Fig. 11 is aschematic diagram of a typical cathode follower gate;

Fig. 2 is a block diagram employed tore present the "triQ a Fig. 15 is aschematic diagram of a typical and gate; Fig. 16 is a block diagramemployed to represent the and gate shown in Fig. 15; j

Fig. 17 is a schematic diagram of a typical delay circuit;

Fig. 18 is a block diagram employed to represent the delay circuit shownin Fig. 17;

Fig. 19 is a schematic diagram of a typical flip-flop circuit;

Fig. 20 is a block diagram employed to represent the. flip-flop circuitshown in Fig. 19; Fig. 21 is a schematic diagram of a typical Schmidttrigger;

Fig. 22 is a block diagram employed to represent the Schmidt triggershown in Fig. 21;

Fig. 23 is a block diagram of -a typical shift register; Fig. 24 is ablock diagram of a typical cascade binary counter;

Fig. 25 is an overall block diagram of the computer; Fig. 26 is aschematic drawing of the Memory Drum; Fig. 27 is a schematic diagram ofa typical transducing head; I

Fig. 28 is a block diagram of the Clock Pulse Genetator and- Clock PulseDistributor;

Fig. 29 is a schematic diagram of a typical Reading:

Amplifier and the Interpreter;

Fig. 30 is a diagram of certain wave forms in the Interpreter.

Although the following description of a specific em-" bodiment of theinvention often refers to exact values, as regards numbers of stages ina register, pulse repetition rates and the like, it is to be understoodthat these values are merely illustrative.

without departing from the scope of the invention.

NUMBER SYSTEM The computer, some of whose circuits are hereinafterdescribed, is a digital computer, as opposed to an analog computer,i.e., it processes and stores representations of discrete digitalvalues. These values are expressedyin thecomputer, in variousrepresentations of theconventiona-l binary'system of notation. Theconventional binary system employs only the digits 0 and 1, any ordinaldigit 0 having an equivalent decimal value of 0 and any ordinal 'digit 1having an equivalent decimal value of 2"- where n is the order number.For ease of under standing, binary values stored or processed in thecomputer will often be referred to as their decimal equivalents I in thefollowing description.

BINARY VALUE REPRESENTATIONS a change in the direction of magnetizationoccurs only.

where there is a change in value as between two successive digits.

A second. form of value representation is employed in.

the Reading Amplifiers, wherein a positive pulse repre' Patented. May19, 1959 Fig. 13 is a schematic diagram of a typical pentode Such valuesmay be varied,- thereby adapting the invention to specificrequirements,'

seats a change in digital value from to 1, as between two successivedigits, and a negative pulse represents a change in digital value from 1to 0. Obviously, the polarities of these two pulses may be reversed, aslong as they remain opposite each other. 7, I

Athird form of value representation is employed in the Transfer Busseswherein a pulse on a first bus representsal) and a pulse on a second busrepresentsa 1. These pulses may be either positive or negative,depending onthe. polarity of pulses required for operating a particular'computer circuit.

For convenience of description, the pulses which represent individualbinary digits, and the groups of pulses which represent multidigitbinary numbers, will often be referred to hereinafter as the respectivedigits or multidigit numbers themselves.

SERIES OPERATION The digital computer which embodies the presentinvention is primarily a serial computer, ie, successive digits of amultidigit binary number are expressed seriatim while they are beingtransferred between circuit units of the computer.

TIMING The computer which employs the present invention is timed by aspecial Memory section which isdesignated the Clock Track, and whichgenerates periodic timing signals. These signals ultimately control aClock Pulse Distributor which, along with the Clock Track of Memory,will bedescribed in detail hereinafter. The output of the Clock PulseDistributor comprises four sequential control pulses, designated CP-l,"CF-2, CF-3 and OP-4, respectively, followed by a train of twenty-sixpulses, designated operating pulses or OPs. The pulse pattern of fourCPs followed bytwenty-six OPs is repeated cyclically throughout thecomputer operation. Each of the four CPs is transmitted on a separateoutput lead from the Clock Pulse Distributor to the various compntercircuits which require a control pulse at that time for any of a numberof control operations, described hereinafter. Each trainofOPs istransmitted on a fifth output lead from the Clock Pulse Distributor tovarious computercircuits for causing shifting operations or the like.The successive pulses in a train of OPs may be gated to represent therespective digits of a multidigit binary number, in which case theresulting number contains twentysixdigits and ,is designated a word. 7

,Thejtime interval between two successive digits of a word is designateda digit interval, and has a duration of a'pproximately fivemicroseconds. Because of several delay circuits employed in the presentinvention, a pulse representing a dig'it may occur at any time duringits relatedjdi-git, interval. The expression word interval will be.u'se.d to.designate a timeperiod embracing the thirty digit, intervalswhich include each set of four CPs and the related train of twenty-sixOPs.

CIRCUIT ELEMENTS In general The following circuit elements areintendedtoillustrate the types of basic elements which are employed as building.blocks. in the present invention. The specific elements shown anddescribed are by no means the only ones of their types that can beincorporated successfully into the. circuits described, 'but eachelement described has been found to operate reliably in the circuitswhere it is used.

Triode amplifier One of the circuit elements employed in the presentinvention is a triode amplifier, an example of which is showniri'Fig. 1. Input signalsare applied to the grid of the amplifierthrough'a terminal 10. The gridishcori nected througha terminal C to asource of bias potential. The potential of'terminal C can be chosen lowenough to normally bias the tube below cutoff for class B or class Coperation in which case only positive input pulses are amplified.Alternatively, the potential of terminal C can be chosen high enough tonormally bias the tube to conduction for class A operation, in whichcase both positive and negative input pulses are amplified. Outputsignals from the amplifier are derived across a resistive anodeimpedance 11 through an output terminal 12. It is well .known that theoutput signal from such an amplifier is reversed in polarity from theinput signal. Fig. 2 illustrates the block representation of the triodeamplifier, as shown in the accompanying drawings.

Phase inverter A modification of thetriode amplifier is a phaseinverter, an example of which is shown in Fig. 3. The phase inverter isidentical to the triode amplifier except that its output signals aretaken from a pair of terminals 14 which are connected to opposite endsof the secondary winding of atransformer 13. The primary winding oftransformer 13 constitutes the anode impedance of the triode. Byconnecting a selected one of the terminals 14 to a reference potential,the remaining terminal 14 may be, employedfor delivering an outputsignal either of the same polarity as the input signal or of oppositepolarity, depending upon whichterminal 14 is connected to the ref erencepotential. If a terminal 14 is used fordelivering a, signal of the samepolarity as the input signal, a tenninal connected directly to the anodemay be usedfor deliverin g'an outputsignal of opposite polarity.Alternatively, the secondary winding of transformer 13 may be c entertapped to a reference potential, and both terminals 14 may then 'beemployed, thereby providing two output signals of opposite polarity.Fig. 4 illustrates a block diagram of the phase inverter as shown in theaccompanying drawings.

Cathode follower A further circuit element employed in the presentinvention is a cathode follower, an example of which is shown in' Fig.5. The cathode follower is a triode current amplifier which receivesinput signals applied to its grid through an input terminal 15, andwhich delivers output signals, in phase with the input signals, across acathode impedance 16. The cathode follower, like the triode amplifier,can' be biased for either class A operation or for class Bor Coperation, depending on the value of a bias potential which may beapplied to the grid through a te'rminal C. Fig. 6 illustrates the blockdiagram' of the cathode follower as shown in the accompanying drawings.

Diode gate invention is a diode gate, an example of which is shown in'Fig.7. This gate includes a diode 18 which is oriented to tr ansmit onlynegative pulses from an input terminal 19 to an'output terminal 20. Inorder for a diode to transmit a negative pulse, however, the potentialof its cathode must fall below the potential of its anode for thedurationof the pulse. Therefore, negative input pulses may be preventedfrom passing through a diode by maintaining. the potential of .itscathode higher than that of its anode by an' amount at least equal tothe amplitude of the inputpulses.. The diode gate shown in Fig. 7 isadapted for selectively blocking or passing negative pulses bymaintaining the anode of diode 18 at a fixed bias potential C and byapplying a selectively high or low bias potential to its cathode througha potential divider comprising an arming terminal 21 in series with afirst resistor 22, a'junction 23 connected to the cathode, a secondresistor 24 and a source of bias potential Cl. A selectively high orlowpotential may 'be applied to the arming" terminal 21 by any ofseveral means, such as by assists;

tial, junction 23 is at a potential which is sufiiciently high forblocking the negativeinput pulses applied to terminal 19, and the diodegate is said-to be closed. When terminal 21 is at its low potential,junction 23 is at a potential which is sufi'iciently low fortransmitting the negative input pulses, and the gate is said to bearmed. Fig. 8 shows the block form of the diode gate as used in theaccompanying circuit diagrams. In Fig. 8, as well as in the remainingblock diagrams, a control lead is shown as a broken line and a pulselead is shown as a solid line. Therefore, in Fig. 8 the arming leadconnected to terminal 21 is shown as a broken line, and the input andoutput leads are shown as solid lines. It is noted that the diode gate,as well as the cathode follower gate hereinafter described, can beemployed for gating DC. potential levels as well as pulses. In suchcases, the input and output leads are shown as broken lines in the blockrepresentations of the gates. For the purposes of the present invention,a square gating pulse of relatively long duration will be treated as anadjustable D.C. gating potential.

Triode gate A second type of gate employed in the invention is a triodegate, an example of which is shown in Fig. 9. This gate comprises asimple triode amplifier of the type previously described in connectionwith Fig. 1, having its control grid biased through the potentialdivider including arming terminal 21 (Fig. 9), resistor 22, junction 23,resistor 24 and terminal C1. The triode gate is adapted to selectivelypass or block positive signals applied to its input terminal 10. Thebias potential C1 and the arming potentials applied to terminal 21 arechosen such that when terminal 21 is at its low potential, the gridpotential of the amplifier is below cutoif level by an amount exceedingthe amplitude of the positive signals applied to terminal 10, and thegate is closed. When terminal 21 is at its high potential, the gridpotential of the amplifier is slightly below cutoff, thereby arming thegate for amplifying positive signals applied to terminal 10. Fig. 10shows'the block representation of the triode gate, as employed in theaccompanying circuit diagrams.

Cathode follower gate A third type of gate employed in the presentinvention is a cathode follower gate, an example of which is shown inFig. 11. This gate includes a cathode follower of the type described inrelation to Fig. 5. The cathode follower gate is armed or closed by arelatively high or low potential applied to its grid through terminal(Fig. 11), and receives input signals applied to its anode through aterminal 25. The cathode follower conducts and pro.- duces an outputsignal at terminal 17 only when both input terminals 15 and 25 are atrelatively high potentials. Fig. 12 illustrates the block formof thecathode follower gate, as employed in the computer circuit diagrams.

Pentode gate A fourth type of gate employed in the present invention isa pentode gate, an example of which is shown in Fig. 13. In this gate,the arming terminal 21 is connectedto the suppressor grid of a pentode,and positive input pulses are applied through the input terminal 10 tothe control grid. The gate is normally closed by maintaining terminal 21at its low potential, and a positive pulse applied to terminal 10 failsto cause the pentode to conduct. On the other hand, if terminal 21 is atits high potential, the gate is armed and the positive pulse applied toterminal 10 is amplified in the pentode to produce an output signal aspreviously described in relation to Figs. 1 and 3. Fig. 14 illustratesthe block form of pentode gate, as employed in the accompanying circuitdiagrams.

' "And gate Any of the previously described gates can be modified" toform an and gate, which is identical to its'related diode, triode orpentode gate except for the 'armingcircuit which provides for two ormore arming inputs All of the arming inputs of the and gate must be atahigh potential in order to arm the gate.

Fig. .15 shows a pentode gate modified to form an and gate. Thearmingcircuit has two or moreinput; terminals 21, each'of which is connectedthrough a respective diode 26 to the suppressor grid of the pentode. Thesuppressor grid is connected to +B'through'a resister 27; therefore, ifany terminal 21 is at a low po tential, it receives current'through itsrelated diode 26 and the resistor 27, thereby causing a potential dropacross resistor 27. This maintains the suppressor grid at a lowpotential and the gate is closed. If all of'the arming" terminals 21 aremaintained at a high potential, there is substantially no current flowthrough resistor 27 and the suppressor grid is at a high potential,thereby arming the gate. Fig. 16 illustrates the block diagram that'isemployed in the accompanying drawings to represent an and gate.

Delay circuit A further circuit element employed in the invention is adelay circuit, an example of which is shown schematically in Fig. 17 asa distributed parameter delay line of the type disclosed in Fig. 5 ofU.S. Patent No. 2,467,857, issued April 19, 1949, to J. H. Rubel, etal., to which reference is made for a full description. It is to beunderstood that other delay circuits, such as lumped parameter delaylines may be employed. Pulses applied to' an", input terminal 28 of thedelay line are delayed a few microseconds or a fraction of amicrosecond, and appear; at an output terminal. The block representationof a delay circuit is shown in Fig; 18.

Bistable circuit A further element employed in the present invention isa bistable "circuit such as the well-known Eccles-Jordan triggercircuit, or flip-flop, described in Theory and Application of ElectronTubes, by H. J. Reich. In one of its simplest form, a flip-flopcomprises two triode vacuum tubes with the grid of each tubecross-coupled to the anode of the other tube through a respectivenetwork comprising a resistor in parallel with a capacitor. One ofthetwo tubes is always conducting while its companion tube isnonconducting, thereby providing a circuit having two stable operatingstates.

A modification of the Eccles-Jordan circuit is shown in Fig. 19, andcomprises two triodes 30 and 31, shown for convenience as the two sidesof a twin triode. When the left hand section 30, hereinafter referredto. as the 0 side, is conducting, the flip-flop is said to be reset;when theright hand section 31, hereinafter referred to as the 1 side, isconducting, the flip-flop is said to be set. Negative pulses may beapplied through a symmetrical" input terminal 32 and a respective diode33 to the grid of each section 30 and 31. Each symmetrically appliedinput pulse reverses the state of operation of the flip-flop in a mannerwell known in the art. If the orientation of each diode 33 is reversed,the flip-flop can be made to respond to positive, rather than negativepulses. Alternatively, an input pulse may be applied through a set inputterminal 34 or a reset input terminal 35 A negative pulsethroughterminal 34 sets the flip-flop if it does not already stand at 1, whilea negative pulse through terminal 35 resets the flip-flop if it is notalready standing at 0. On the other hand, a positive pulse applied toterminal 34 or 35 causes the flip-fiop to be reset or set, respectively.A diode (not shown) may be inserted in series with each terminal 34 or35. If each such diode is oriented to transmit only negative pulses. tothe q grid of its related flip-flop section, then terminals or 35 aredesignated the reset and set" terminals, respeetiyely in, @QCOIdanpe,vvith the previously described effects ofnegativepulses applied tothese terminals.

Thefiip-fiop is adapted to control or operate other dei by eans of thechanging. potential levels on the anodes of its two sections, When theflip-flop stands'at 0, the potential of the anode of; section 3Qvisrelatively low \vhilethe potential of; the. other anode is relativelyhigh, the;converse being true when the flip-flop stands at 1. The ghangeof anode potentials of a flip-flop may be emplpyedfor controllingany-ofthe previously described gates by connecting the appropriateanodeof the flip-flop to the arming terminal ofthe gate through aflip-fiopoutput terminal 36. It is also noted that when a fiip-fiop isreversedfrom one of its states to the other, a potential rise appears-at one ofits output terminals 36 and a potentialdrop appears at theot-her. .Ihesepotential changes may be employed for operating otherflip-fiops or thelike. l n. the block diagrams andin the descriptions of the accompanyingcircuits, the following conventional is adhered-to regarding theflip-flap outputflterminals 36: a gate which. is armed by the side, orthrough the -0 side output terminal of a flip-flop, has its arming.terminal connected to that terminal '36 whose potential is appropriatefor armingthe gate when the flip-flop stands at 0. A similar conventionis used in relation to a gate which is armed by the 1 side, or throughthe 1 side output terminal of a flip-flop. If a signal from the 0 sideoutput terminal is employed for operating a next flip-flop, the outputsignal is understood to be taken from that terminal '36 which delivers avoltage change in the appropriate direction for operating the nextflip-flop when the first flip-flop is reversed from 0 to 1. A similarconvention is used in relation to a flip-flop which is operated responseto a changeof state, from 1 to 0, of a previous flip-flop. The blockrepresentation of a flip-flop is shown in Fig. 20.

Schmidt trigger Another element employed in the invention" is 3 aSchmidt trigger, an example of which is shown in Fig. 21. This circuitis employed as a pulse generator, and produces an output pulse having aduration which depends upon the duration of the input signal.

Referring to Fig. 21, the Schmidt trigger comprises two triode vacuumtubes 50 and 51, which are shown for convenience as the two sections ofa twin triode. The anode of section 50 is cross-coupled to the grid ofsection 5 1, and both cathodes are returned to a source of referencepotential through a single pair of resistors 52 and 53 arranged inseries, Section 51 is normally biased to conduction, while section 50 isnormally biased to ,nonconduction. Positive input signals are applied tothe grid of section 50 through an input terminal 54. Whenevertheamplitude of the input signal is sufiiciently highto. bias section 50 toconduction, the anode voltage of section v50 drops, thereby coupling anegative pulse to the grid. of section 51 for cutting oif the lattersection. When the amplitude of the input signal again drops below thecutoff potential for section 50, that section is cutoff and its, risinganode potential causes section 51 to againconduct. The changes fromconduction to nonconduction, and vice versa,.of section 51 are rapid,and the. anode potential of that section therefore rises and fallssharply, producing a substantially square positive pulse at an outputterminal 55. The block representation of the Schmidt trigger is shown inFig. 22.

Shift register I Afurther element employed in the invention is a shiftregister, an example of which is shown in Fig 23. This registercomprises a plurality of value-storing flip-flop stages 78(l to 78(n),the number of stages being determined by the number of digits in thelongest binary word thatis to be stored in the register. The stages arearrality of flip-lop stages 95(1) to 95(n).

ranged in the drawing withthe least significant stage-at the top and themost significant stage at the bottom. The register is adapted to receivea binary word; digitby-digit, into the most significant stage, toshiftthe word digit-by-digit through the successively less significantstages, and to transmit the word-digit-by digit from the leastsignificant stage to any desired unit of the computer.

Referringto Fig. 23, each flip-flop 78 controls apair of shift gates 79and 80. Each gate 79 is armed when its related stage stands at "Whileeach gate 80 is armed when its related stage stands at 1. For shifting,consecutive OPs are applied through a terminal 83 to a shift bus 84which transmits the OPs to the input of each shift gate 79 and 80. Eacharmed gate 79 or 80 transmits each OP to the next stage and sets orresets that stage accordingly. Values may be entered into the shiftregister from a Os input terminal 85 and a ls input terminal 86 whichare connected, respectively, to the reset and set input terminals of themost significant stage. Alternatively, values may be entered into theregister through the ls input terminal 86 alone, in which case the shiftterminal 83 is connected to the reset input of stage 78(n) by a lead 87.for resetting .that stage to 0 during any digit interval in whichno lsinput pulse is received at terminal 86. The word standing in theregister may beshifted out of, the last register stage, i.e., stage78(1), through a. US output terminal 88 and a. ls output terminal89which. constitute the output terminals of the last stage shift gates79(1) and 80(1), respectively.

Binary counter A final element employed in the present invention is a,multi-stage binary counter, an exampleof which is shown in Fig. 24. Thebinary counter comprises a plu- Input pulses are appliedv symmetricallyto the leastsignificant stage, i.e.,,stage 95(1),. through a terminal96, and each input pulse reverses stage 95(1). Each stage has a 0 sideoutput terminal 97 and a '1 side output terminal 98 by means of whichthe stages are connected in binary cascade, i. e., one of the outputterminals 9.7,.or 98 ofeach flip-flop stage except the last is connectedto the symmetrical input of the next stage. In the circuit shown in Fig.24, the 1 side output terminal 98 ofeach stage is connected to thesymmetrical input of the next stage; therefore,

when each stage reverses from its 1 state to its 0 state, a sharpnegative potential change is transmittedfrom that stage to thesymmetrical input of the. next stage, thereby reversing the state of thelatter. -Through this arrange ment, the input pulses are counted inincreasing order,

and the circuit operates as an upcount binary counter. By connecting the0 side outputterminal 97 0f each stage tothe symmetrical input terminalof the next stage, the circuit can be made to operate as a downcountbinary counter, i.e., each input pulse applied to stage (1).

Computer sections v The computer in which the present invention isemployed may be considered, for convenience of description, ascomprising six principal sections, as follows:

1. Memory section;

. Timing section;

. Transfer section;

. Arithmetic section;

. Address section; and Program section.

GUI-bulb) Memory section i Referring to the overall: block diagram ofthe com- 15" puter, shown in Fig. 25, the Memory Section includes asawscontinuously rotating Memory Drum 100. The Drum 100 has a continuousmagnetizable surface which, due to the location of sixty-fourtransducing heads adjacent the Drum and spaced along its axis, may beregardedas having sixty-four circumferential .Inforrnation Bands spacedalong the drum axis. "Each Information "Band cooperates ,with arespective Reading Head,110() to 110(63) for receiving writingsignalsfrom and trans mitting reading signals tothe Transfer Section,hereinafter described. Each Information Band is divided into,

sixty-four sectors which arev spaced in the direction of:

Each Information Band has a single gap in its otherwise continuous arrayof cells, and the gaps in all bands pass simultaneously under theirrelated Reading Heads.- The gapsconstitute .an index position of theMemory Drum from which the sectors in each Information Ban 2 arenumbered.

Timing section The Timing Section includes the previously-mentionedClock Track, which is an auxiliary band on the Memory Drum 100. TheClock Track contains a number of cells equal to the total number ofcells in each Information Band, viz., 64 30=1920cells. The clock cellsare evenly spaced along the Clock Track, and, there is a single gapcorresponding'to the gap on each Information Band. The clock cells arepermanently magnetized in a predetermined pattern, hereinafterdescribed, and 'cooperate with an auxiliary transducing head 110(64);

designated the Clock Head, to energize the latter for producing arepetitive timing signal. The timing signal is-transmitted to a ClockPulse Generator 120' which generates a sharp clock pulse at thebeginning of each digit interval and an index pulse during the singlegap in the Clock Track cells. The clock-pulses and index pulse aretransmitted to a Clock Pulse Distributor: 130,"

the output of which comprises a repetitive'cycle of four (CPs followedby a train of twenty-six OP s, for timing the computer operations.

Transfer section The'Transfer Section includes a respective ReadingAmplifier 150(0) to 150(63) for cooperation with'each of the ReadingHeads 110(0) to 110(63). Each Reading Amplifier is repetitivelyenergized by the signals stored in the related Memory band and amplifiesthese signals.

Amplified reading signals are ordinarily blocked, but during a readingoperation the reading signals from a selected Reading Amplifier 150(0)to 150(63) are gated to an Interpreter 200. p

The Interpreter has two primary functions. First,

the reading signals that it receives are of varying 'duration andamplitude. The Interpreter shapes these si'gnals and times them with theproper clock pulses. The

shaping and timing operation requires a period of two digit intervals;therefore, the 'output from the Interpreter is delayed by two digitintervals from the input.

In order forthe Interpreter output to be timed properly with the CPs andOPs, it is necessary for. each of its input signals to be received twodigit intervals prior to the generation of the related clockpulse. Toaccom-v plish this, all digits of a word written into Memory are writtentwo digit intervals aheadof their related OPs, by means described inthepreviouslymentionedapplication Serial No. 458,473; Thercfore, thefirst two digitsof the word are written coincident with (DP-3 and CR4,respectively,.the last twenty-four digits of the word are writtencoincident with the twenty-four OPs of the related train, and the lastthree cells in each Memory sector remain unused.

The second function of the Interpreter 200 is to change the-form of thereading signal. It is recalled that a reading signal from Memory occursonly when there is a change in value from 0 to l, or vice versa, asbetween two successive cells in a band. This form of signal is convertedby the Interpreter into a second form wherein a discrete pulserepresents each digit 0 to l. The 0s and 1s pulses are transmitted bythe Interpreter to the appropriate Os or ls Transfer Busses.

The remainder of the Transfer Section, as well as the entire Arithmetic,Address and'Program Sections, is described in the previously-mentionedapplication Serial No. 458,473, and forms no part of the subjectmatterof the present invention.

MEMORY SECTION Memory drum The Memory, shown schematically in Fig. 26,com,- prises a drum .101 which is mounted by hubs such as 102 on a shaft103, the shafts being driven by a motor (not shown). The drum comprisesamain body 104 which may be formed of aluminum or other rigid ma-.terial, and which is coveredby a thin coating 105 of magnetizablematerial, such as magnetic iron oxide in-. vested in a plastic base. Animproved process for coat-. ing the drum is described and claimed in thecopending applicationSerial No. 492,222, filed March 4, 1955, by WayneEX, Willis and George B. Greene.

The magnetizable drum surface may be considered as comprising sixty-fivecircumferential bands spaced along the drum axis, one band constitutingthe Clock Track and the remaining sixty-four bands constitutingtheInformation Bands. As previously described, each band may beconsidered as comprising sixty-four substantially equal sectors spacedin they direction of drum rotation, with each sector, divided intothirty cells also arranged in the direction of drum rotation. Each band,including the Clock Track, has a single gap in its otherwise continuousseries of cells. The gaps in all bands simultaneously pass their relatedReading Heads or Clock Head, and the sectors in each band may be con--veniently'countedby starting from the gap.

Each cell in-the Information Bands may be magnetized to saturation ineither of two opposite directions, thereby representing the respectivebinary digits 0 and 1. The entire Clock Track is permanently magnetizedin a pattern representing alternate 0s and 1s, for reasons hereinafterdescribed. The. Clock Head (64) is located adjacent the path of theClock Track and is energized ,by the magnetized pattern of the ClockTrack for transmitting to the Clock Pulse Generator (Fig. 35) a timingsignal when the leading edge of each cell on the Clock Track passes theClock Head 110(64) (Fig. '26). Arespective Reading Head 110(0) to110(63) cooperates with each Information Band on the drum and isconnected to a respective Reading Amplifier (0) to'150(63). i

' Reading heads I ='A typicalReading Head 110'is'shown in Fig. 27. TheHead comprises a magnetic core 111 which is substan tially triangular-inshape and which has a gap 112 located at one corner of the triangle. Amagnetizing coil 113 'is wound on that leg of the core which is oppositegap 112. The coil 113 is grounded at one end and has an output terminal114 at the other end which is connected to a related Reading Amplifier150. The gap 112 is located adjacent the path of the related band ofdrum 101, see also Fig. 26) for cooperation therewith.

A particular cell transmits a reading signal only when it underlies gap112. When there is a reversal in the direction of magnetization of thedrum surface underlying gap 112, the change of flux induced in core 111causes current to flow through winding 113 in a direction which isdetermined by the direction of change of magnetization of the magneticmedium.

An improved Reading Head, which may be employed in the presentinvention, is disclosed and claimed in the copending application SerialNo. 297,441, filed July 7, 1952, by George B. Greene.

TIMING SECTION Clock pulse generator The Clock Pulse Generator receivestiming signals from the Clock Head 110(64) (Fig. 26), and amplifiesthese signals to form clock pulses. The clock pulses are employed togenerate an index signal which, together with the clock pulses, istransmitted to the Clock Pulse Distributor.

The timing signals from the Clock Head are received by the Clock PulseGenerator 120 (Fig. 28) at a terminal 121. Even though a substantiallysquare wave (alternate s and 1s) is employed for writing the ClockTrack, and therefore the signal output of the Clock Head would ideallybe the derivative of a square wave, i.e., alternate positive andnegative pulses, the resolution properties of most commercially availClock Heads are such that the clock signals received at terminal 121 maybe substantially sinusoidal. The clock signals are transmitted through atwo-stage amplifier 122 to the input of a Schmidt trigger 123. Trigger123 may be of the type shown in Fig. 21, except that it has atransformer out-' put impedance which differentiates the square waveoutput signals. The output from one transformer terminal of the Schmidttrigger is therefore a series of alternating positive-and negativepulses, and the output from the other terminal of the transformer is acomplementary series of alternating negative and positive pulses. Eachof the two outputs from the Schmidt trigger 123 (Fig. 28) is transmittedthrough a respective diode 124 which is oriented to pass only positivepulses. The outputs of the two diodes 124 are joined, their combinedsignal output comprising a series of positive pulses. There are twooutput pulses from diodes 124 during each complete cycle of the timingsignal from the Clock Head, i.e., one positive pulse corresponding toeach cell of the Clock Track. The combined output of diodes 124 isamplified in a two-stage amplifier 125, the output pulses of amplifier125 constituting the clock pulses which are employed in the presentcomputer. The clock pulses from amplifier 125 are transmitted through aterminal 215 to the Interpreter (Fig. 25), and are also applied to theinputs of a pair of gates 135 and 136 (Fig. 28), hereinafter described.

The clock pulses from amplifier 125 are also transmitted through a pairof amplifiers 126 and 127, arranged in series. The input to amplifier127 is connected to a source +C of positive grid bias potential througha capacitor 128 in parallel with a resistor 129. The positive clockpulses from the output of amplifier 125 are inverted by amplifier 126and charge capacitor 128 negatively for maintaining amplifier 127normally nonconducting. However, when the previously-described gap inthe Clock Track passes the Clock Head, the generation of clock pulses isdiscontinued for a short time, and capacitor 128 discharges throughresistor 129, thereby applying +C potential to the input grid ofamplifier 127 and causing the latter to conduct. When the generation ofclock pulses is recontinued, capacitor 128 is again charged negatively,and cuts olf amplifier 127. The output from amplifier 127 is therefore asquare negative pulse, hereinafter designated an index pulse, since itis generated once during each rotation stages 132(2) to 132(5).

of the Memory Drum and at a time when the latter is at an indexposition.

Clock pulse distributor The index pulse from the output of amplifier 127(Fig. 28)is transmitted through a diode 131(2) to the set input of aflip-flop 132(2), constituting the second stage of a five-stage binarycounter which may be of the type shown in Fig. 24. The index pulse isalso transmitted through each of a pair of diodes 131(4) and 131(5)(Fig. 28) to the respective set inputs of the fourth and fifth stageflip-flops 132(4) and 132(5) of the counter. Therefore, the index pulsesets the binary counter to the value 11010 which is equivalent to thedecimal value 26. The previously mentioned gate 135, which isinterrogated by the clock pulses from amplifier 125, is an and gatewhich is armed through a series of diodes 133(2), 133(4) and 133(5) bythe concurrent 1 states of flip-flops 132(2), 132(4) and 132(5).Therefore, gate 135 is armed when the index pulse sets the second,fourth, and fifth stages of the counter to 1, and the first clock pulsewhich is generated following the index pulse is transmitted through gate135.

The output of gate 135 is connected to the shift bus of a five-stageshift register which may be of the type shown in Fig. 23. Each stage ofthe shift register comprises a respective flip-flop 142(1) to 142(5)(Fig. 28). The output of the last stage of the shift register isconnected to the input of the first stage, so that any word standing inthe shift register may be recirculated. The index pulse from the outputof amplifier 127 is also transmitted through a diode 141(1) to the setinput of shift register stage 142(1), and through a series of diodes141(2) to 141(5) to the reset inputs of stages 142(2) to 142(5) of theshift register. Therefore, the index pulse enters the binary Word 10000into the shift register. The first clock pulse which is transmittedthrough gate 135 to shift bus 140, following the index pulse, shifts thedigit 1 from stage 142(1) to 142(2), and each stage except stage 142(2)receives a 0 from its preceding stage. The 1 side output terminal ofstage 142(1) is connected through an amplifier 144(1) and a phaseinverter 145(1) to a pair of output terminals CP-l. When stage 142(1) isreversed from 1 to 0 in response to the first clock pulse following theindex pulse, the voltage change of its 1 side output terminal istransmitted through amplifier 144(1) and phase inverter 145(1), andpulses of opposite polarity appear at the two output terminals CP-l.Therefore, the first clock pulse which follows each index pulsegenerates both a positive and a negative output pulse at terminals CP-l,and either of these pulses, depending upon the polarity desired, may beemployed as CP-l.

The second clock pulse following the index pulse is also transmittedthrough gate 135 to shift bus 140, thereby causing the digit 1 standingin stage 142(2) to be shifted to stage 142(3), and the consequentvoltage change in the 1 side output terminal of stage 142(2) generatesthe second control pulse CP-2 in the same manner as CP-l. Similarly, thethird and fourth clock pulses, following each index pulse, are employedfor shifting the digit 1 standing in stage 142(3) to stages 142(4) and142(5), in turn, thereby generating third and fourth control pulses CP3and CP-4, respectively. The external use of control pulses CP-l to CP-4is described in the previously-mentioned application Serial No. 458,473.

CP-4 is transmitted through a lead 146 and a series of diodes 134(1) to134(5) to the set input of counter stage 132(1) and to the reset inputsof the remaining counter CP-4 thereby sets the counter to the value00001, closing gate 135 to prevent subsequent clock pulses from beingtransmitted by that gate to the shift bus 140. Therefore, after thefourth clock pulse following each index pulse, the value 1 stands instage asses-7a clock pulses,

. The previously-mentioned gateflti, which interro-i gated by each clockpulse from the output of amplifier 125, is armed .by the ;1 s ide ,of;stage 142 5.),, and is. therefore armed following the generation of CF 4The output of. gate 136 is. connected through .an amplifier 137 and alead 138 tqthesymmetrical input of the first stage 132(1) in, thebinary'counter. Therefore, after-the first four clock pulses,.following,e ach index pulse, have been. employedtov generate control pulses,subsequent c 1ock pulses are transmitted through gate 136, amplifier 137and 1eadi138 to the symmetrical input of the first counter stage 132(1),thecounter' having been. preset to the value 00001'as-previously'descfibed. When twenty-five clock pulses have'inlthismannerbeen introduced into the sym metrical input-.1of s tage.132(1),the counter stands at the value .11010 which, as .previously described,causes the counterto arm gate1135. The twenty-sixth pulse which isentered-.into the counter advances .itscount to the binary equivalent of"2.7, and is also transmitted throughv digit l-'is shifted..from stage?142(5) to'stage 142(1),-

gate 136 :isclosed. It'is noted,- however; that gate 136 was armedduring a periodin which it transmitted, twentyfier;137,.-in addition. tobeing connected to ,the symmetrical input ofy:counter' stage --.132(1),1is, alsov connected through-a cathode-follower 147, to an outputterminal OP. Therefore, twenty-isixipulses are transmitted toterminalOP-rduringeachmbrd interval, andthe-train of twenty-six pulsesaareemployed .as operating pulses. or

I I 1 {.Rading ampl fi eta orthe previously described-Reading Heads 1100 to 110(63) (Figs. 25' and 26) transmitsits reading signals toarespective Reading'Amplifier' 1501(0) to 150(63) example of which isshown in Fig. 2.9. The output terminal 114 of the coil 113 'of eachReading Head 110 is coupled fromone end of winding 113 to the grid inputqffaclas's triode amplifier 162. -The output of amplifier; 1:6 2"iscoupled'tothe input of a cathodefollower' gate 164 whichis normallyclosed. Gate 164-1'nay be; aimed" through its arming tenninal' 165 bythe 'applica-' tioii (if asuitable voltage to that terminal. Thisvoltage may-be applied, 'for e'xample, when the proper memory bandhasbeen selected for -readin'g,jin the manner described in thepreviously-mentioned applicatiom Serial No.45;8 ,473. ,When gate 164'isarmed, the mean applied to its -inputtrcgrnamp'lifier' 162 aretransmitted through-its output; and a lead 204 to an input of theInterpreter; Interpretrinputs from the other sixty-three ReadingAmplifiers fare indicated at; 166(1) to 166(63) '1" Interpreter It hasbeen: shown that a change from 0sto 1, or vice versa, as betweensuccessive digitalvalues'in a Memory band, is represented by areversalof; magnetic state from one region of saturation to .the other. :lt hasalso been shown that the signal output from a Reading Head comprises.the derivative of the written signal, i.e., a positive pulsewhenandonlywhen there is a change from, 0 to 1 as between the digits stored in twoconsecutive cells 'of the related Memory band, and a negative 'puisewhen and only when. there is a similar change from 1 to 0. However, ithas been shown that words on the Transfer 3 Busses appear in the form ofone pulse for each digit 0 or 1, rather than one pulse for each changein value. The Interpreter is provided for receiving the first form ofsignals from Memory, and for converting them to equivalent signals ofthe second form for transmission to other circuits through the TransferBusses.

If uniform signals are available from Memory, the convertingprocess maybe performed quite simply. Such uniform signals are available, forexample, when the Memoryband which is being read contains a regularpattern such as alternate 0s and 1s. However, each Information Band ofMemory contains randomly arranged 0s and ls, and it has been found thatrandomly'arranged 0s and 1s result in aperiodic output pulses from aReading Amplifier, positive pulses having the shapes shown in in- Fig.,30 while negative pulses are similarly shaped but of opposite polarity.Each 'of the five pulses shown in Fig. 30. represents a change in the.recorded value at a time corresponding to the center one of the threeclock pulses shown. It will be seen that value pulses III, IV and V areof such duration that they might be mistaken as having occurred incoincidence with the first or third clock pulse, rather than the secondclock pulse, thereby,

of a-Reading Amplifier when the value in the related Memory bandisalternating between 0's and ls, is Olf relativelylow amplitude and wouldnot be'detected at all if;onl y .the topsof the pulses were detected.There-- fore, means must be provided for interpreting all of thepossible shapes of output pulses from the Reading Amplifiers, and forconverting them to uniform and properly timed pulses. The Interpreter200, which is shown in Fig. 29, performs the necessary shaping andtiming functions, as followsh The. terminal166 from each ReadingAmplifier (0) to 150( 63) is connected through the previously-mentionedlead 204 to the input of the Interpreter 200. It is recalled thatinformation signals are transmitted [from the output of only one of theReading Amplifiers 150(0) to 150(63) at a time, i.e., from the oneReading Amplifier which corresponds to the selected band of Memory. Itis further recalled that when a band of Memory is selected,

the normally olosed cathode follower gate 164 of the re-.

lated Reading Amplifier is armed. Therefore, the potential of the.terminal 166 from one of the Reading Amplifiers is ,raised at the timethe. band is selected and tends to introduce a strong spurious signalinto the Interpreter through lead 204 at this time. The spurious signalis prevented in the followingmanner. A read control flip-flop 201normally stands at 0, each CP-l being applied to its reset input. The 0side output terminal of flip-flop 201 is connected to the input lead 204through a cathode follower 202 which has a cathode impedance in commonwith all of the sixty-four cathode follower gates 164. Therefore, whileflip-flop 201 stands at '0, lead 204 'is always at a relatively highpotential,

and when a band is selected, thereby arming a cathode follower gate164,there is substantially no potential rise on lead 204. After the band hasbeen selected, and the related cathode follower gate 164 is armed,flip-flop 201 is set to l for cutting off cathode follower 202.

Each CP-3 is applied to the input of a gate 205, the output of which isconnected to the set input of flip-flop 201. Gate 205 is selectivelyarmed during each reading operation, and the next CP-3 sets flip-flop201 to 1. The

arming terminal of gate 205 may be accomplished, for

15 example, in the manner described in the previously-mentionedapplication Serial No. 458,473.

The input lead 204 of the Interpreter is connected to the input of aphase inverter 208. A typical read signal is shown at the input of phaseinverter 208, and comprises a leading negative pulse and a trailingpositive pulse. The negative pulse indicates a change from to 1 of thedigit value in the selected Memory band, and the positive pulseindicates a subsequent change from 1 to 0 of that value, one or moredigits later. Although a change of digit value from 0 to 1 haspreviously been described as producing a positive pulse output from aReading Head 110 (Fig. 27), amplifier 162 of each Reading Amplifier150(0) to 150(63) (Fig. 29) inverts the reading signal, and cathodefollower gate 164 does not re-invert the signal; therefore, a negativepulse at the input of the Interpreter indicates a change in digit valuefrom 0 to l.

The inverted output from phase inverter 208 is transmitted through anamplifier 209 which again inverts the signal to produce a positive pulsefor each change in value from 1 to 0. The uninverted output from phaseinverter 208 is transmitted through an amplifier 229 which inverts itsinput signal to produce a positive pulse output for each change in theband value from 0 to 1. The output of amplifier 209 is employed forcontrolling the transmission of pulses to the 0s Transfer Bus, and theoutput of amplifier 229 is employed for controlling the transmission ofpulses to the 1s Transfer Bus. The circuit for transmitting pulses tothe Os Transfer Bus is substantially identical to the circuit fortransmitting pulses to the 1's Transfer Bus, and only the former will bedescribed in detail.

The output of amplifier 209 is connected to the inputs of two Schmidttriggers 211 and 212. Trigger 211 is biased to respond to only thatportion of each positive input pulse which has an amplitude higher thanlines a in Fig. 30, while trigger 212' (see also Fig. 29) is biased torespond to that portionof each positive pulse lying above :lines b inFig. 30. Therefore, if a positive input pulse is higher in amplitudethan line a, trigger 211 produces a positive output pulse having a widthequal to the width of that portion of the input pulse which lies aboveline a. Trigger 212 produces a positive square output pulse having awidth equal to the width of each positive input pulse at line b. Thepulse output from trigger 211 arms a gate 213, and the pulse output fromtrigger 212 arms a gate 214.

Clock pulses are received from output terminal 215 of the Clock PulseGenerator 120 (Fig. 28), and are transmitted through a delay line 216(Fig. 29) to the input of gate 213. It is desirable for each clock pulseto interrogate gate 213 at substantially the middle of each output pulsefrom trigger 211. To accomplish this, there must be taken intoconsideration an inherent delay of each reading signal in the ReadingAmplifiers 150 (see also Fig. 25) and in the input section of theInterpreter. Therefore, delay line 216 is provided for delaying eachclock pulse long enough to make it coincide substantially with thecenter of the corresponding output pulse from trigger 211.

The output of delay line 216 is also transmitted through an amplifier217 and a delay line 218, the purpose of which will be hereinafterdescribed, to the input of gate 214 and to the input of a gate 220 whichis controlled by the 1 side of a flip-flop 221. Flip-flop 221 normallystands at 0, each CP-2 being applied to its reset input. The output ofgate 213 is connected to the reset input of flip-flop 221, and theoutput of gate 214 is connected to the set input of flip-flop 221. Theoutput of gate 220 is connected to the reset input of flip-flop 221 andto the reset input of a flip-flop 223 which normally stands at 0, eachCP-3 being applied to its reset input. Gates 213 and 214 and flip-flop221 are employed for selecting the one clock pulse corresponding to thecenter of each information pulse which represents a change in band value16 from 1 to 0. Gate 220 is employed for transmitting the succeedingclock pulse to the reset input of flip-flop 223, which then controls thetransmission of succeeding OPs to the 0s Transfer Bus until the bandvalue changes from 0 to 1.

It is recalled that the input signals to the Interpreter are delayedpart of a digit interval by the Reading Amplifiers, so that each inputsignal to the Interpreter is part of a' digit interval behind itscorresponding clock pulse. An additional delay of a full digit intervaloccurs in the Interpreter before flip-flop 223 is reset to 0 asdescribed above. Therefore, reset pulses applied to flip-flop 223 aredelayed more than one, and less than two digit intervals. By employingOPs for reading out flip-flop 223, as described above, the readingsignals are delayed exactly two digit intervals, and the word pulsetransmission to the Os Transfer Bus is two full digit intervals behindthe, corresponding clock pulses. To compensate for this de-- lay, wordsare written in Memory two full digit intervals ahead of theircorresponding clock pulses, in a manner hereinafter described;therefore, the output from the In-' terpreter 200 is correctly timedwith the OP trains from the Clock Pulse Distributor (Fig. 28).

The 1 side output terminal of the previously-described read controlflip-flop 201 (Fig. 29) arms a gate 207. Each CP-4 (which is synchronouswith the sign digitpulse on the 1s Transfer Bus) and each train of OPsare applied to the input of gate 207, the output of which is connectedto the inputs of a pair of gates 224 and 225. Gate 224 is armed by the 0side of flip-flop 223 and has its output connected through an amplifier226 to the 0's Transfer Bus. Gate 225 is armed by the 1 side offlip-flop 223 and has its output connected through an amplifier 227 tothe 1s Transfer Bus.

The operation of the 0's section of the Interpreter will be describedwith reference to the five possible shapes of pulses which may beapplied to the inputs of Schmidt triggers 211 and 212. Information pulseI (Fig. 30) is a thin pulse of low amplitude. Therefore, trigger 211(see also Fig. 29) does not respond to this pulse, but trigger 212 doesrespond and produces a square output pulse which arms gate 214, gate 213remaining closed. The clock pulse preceding the center of theinformation pulse, hereinafter referred to as the first of the threeclock pulses related to each information pulse is blocked by gates 213,214 and 220. The second clock pulse, i.e., that clock pulse which issubstantially coincident with the center of the information pulse, istransmitted through the armed gate 214 for setting flip-flop 221 to 1,thereby arming gate 220. Although flip-flop 221 is set to 1 by thesecond clock pulse, arming gate 220, the flip-flop requires a definitetime for switching; therefore, the second; clock pulse is blocked bygate 220. The third clock pulse is transmitted through that gate,resetting flip-flop 221 to 0 for closing gate 220, and resettingflip-flop 223 to 0 if the latter does not already stand at 0. Therefore,sub-f sequent OPs from the output of gate 207 are transmitted throughgate 224 and amplifier 226 to the Os Transfer Bus until flip-flop 223 isset to l in a manner hereinafter described.

Information pulse II is of short duration and high amplitude, andenergizes both Schmidt triggers 211 and 212, thereby arming gates 213and 214. However, neither of these gates is armed at the time itreceives the first of the three related clock pulses, and that clockpulse is blocked by both gates 213 and 214 and by gate 220.- The secondclock pulse is first transmitted through gate 213 to the reset input offlip-flop 221 which, however, already stands at 0. The second clockpulse is delayed by delay line 218 and then transmitted through gate214, for setting flip-flop 221 to l and arming gate 220. By the time thethird clock pulse is applied to gates 213 and 214, both of these gatesare closed. However, the third clock pulse is transmitted through gate220, resetting flip-flop 221 to 0 for closing gate 220, and resetting'flipflop 223 to if the latter is not already reset. Thereafter, OPsfrom the output of gate 207 are transmitted through gate 224 andamplifier 226 to the Os Transfer Bus until such time as flip-flop 223 isset to 1.

Information pulse III is of long duration and high amplitude. .It risesabove both potential levels b and a after the first and before thesecond clock pulse, then falls below bevel a between the second andthird clock pulses, and finally falls below level b after the thirdclock pulse. Therefore, pulse III energizes Schmidt trigger 211 toproduce an output pulse having a width which encompasses only the secondof the three clock pulses, and energizes Schmidt trigger 212 to producean output pulse having a width which encompasses both the second andthird clock pulses. The first of the three related clock pulses isblocked by gates 213, 214 and 220. The second clock pulse is transmittedthrough gate 213 to the reset input of flip-flop 221 which, however,already stands at 0. The second clock pulse is thereafter transmittedthrough gate 214 to the set input of flip-flop 221, thereby setting thelatter to 1 and arming gate 220. The second clock pulse is blocked bygate 220 due to the inherent switching time of flip-flop 221. The thirdclock pulse is blocked by gate 213, but is transmitted through gate 220to the reset inputs of flip-flops 221 and 223, as hereinbeforedescribed. The third clock pulse is also transmitted through gate 214 tothe set input of flip-flop 221. The pulses simultaneously applied to thereset and set inputs of flip-flop 221 operate as a symmetrical input andreverse flip-flop 221 to its 0 state, thereby closing gate 220.Subsequent OPs from gate 207 are thereafter transmitted through gate 224and amplifier 226 to the Os Transfer Bus until such time as flip-flop223 is set to l. Information pulse IV is also of long duration and highamplitude. It rises to potential level b before the first of the threerelated clock pulses, then rises above level a before the second clockpulse, and finally falls below both levels a and b before the thirdclock pulse. Information pulse IV therefore energizes Schmidt trigger211 to produce an output pulse having a width which encompasses only thesecond clock pulse, and energizes Schmidt trigger 212 for producing anoutput pulse having a width which encompasses both the first and secondclock pulses. The first clock pulse is blocked by gates 213 and 220, butis transmitted through gate 214, setting flip-flop 221 to its 1 statefor arming gate 220. The second clock pulse is transmitted through gate213, resetting flip-flop 221 to 0 for closing gate 220. The second clockpulse is also transmitted through gate 214 for setting flip-flop 221back to 1 and arming gate 220. Delay line 218 causes sufficient time toelapse after application of the pulse from gate 214 to the set input offlip-flop 221 and before application of the pulse from gate 213 to thereset input of flip-flop 221 for permitting the latter to be completelyreset to 0 before the second clock pulse interrogates gate 220.Therefore, although the second clock pulse is transmitted through gate214 for setting flip-flop 221 to 1, that clock pulse is blocked by gate220 due to the inherent switching time of flip-flop 221. The third clockpulse is blocked by both gates 213 and 214, but is transmitted throughgate 220 to the reset input of flip-flop 221, thereby closing gate 220.The output pulse from gate 220 is also transmitted to the reset input offlip-flop 223, causing subsequent OPs to be transmitted to the OsTransfer Bus in the manner hereinbefore described.

Information pulse V is of long duration and high amplitude. It risesabove potential level b prior to the first of the three related clockpulses, then rises above level a prior to the second clock pulse, thenfalls below level a prior to the third clock pulse, and finally fallsbelow level b subsequent to the third clock pulse. Information pulse Vtherefore energizes Schmidt trigger 211 to produce an output pulsehaving a width which encompasses only the second of'the three relatedclock pulses, and energizes Schmidt trigger 212 for producing .118 anoutput pulse which has a width encompassing all three of the relatedclock pulses. The first clock pulse is blocked by gates 213 and 220, butis transmitted through gate 214, setting flip-flop 221 to l for arminggate 220. The second clock pulse is transmitted through gate 213 forresetting flip-flop 221 to 0. The second clock pulse, after passingthrough delay line 218, is blocked by gate 220, but is transmittedthrough gate 214, setting flip-flop 221 to l and arming gate 220. Thethird clock pulse is blocked by gate 213 but is transmittedsimultaneously through gates 214 and 220 to apply both a set and a resetpulse to flip-flop 221, thereby reversing the latter to 0 in-the mannerhereinbefore described. The pulse output from gate 220 also resetsflip-flop 223 to 0; therefore, subsequent OPs are transmitted to the 0'sTransfer Bus until such time as flip-flop 223 is set to 1.

Flip-flop 223 is set to l in response to each pulse from the ReadingAmplifiers which signifies a change in the band value from 0 to 1. Thecircuit for setting flip-flop 223 to 1 is substantially identical to thecircuit previously described for resetting that flip-flop to 0, andincludes a pair of Schmidt triggers 231 and 232 which are biased,respectively, to respond to that part of an information pulse which liesabove potential levels a and b. The output of the previously describedamplifier 229 is connected to the inputs of both Schmidt triggers 231and 232, it being recalled that the output of amplifier 229 is apositive pulse for each information signal, indicating a change from 0to 1 of the band digit. The clock pulse output from delay line 216 isapplied to a gate 233 which is armed by the output of trigger 231, andthe output ofdelay line 218 is applied to the input of a gate 234 whichis armed by the output of trigger 232. The output of gate 233 isconnected to the reset input of a flip-flop 241 and the output of gate234 is connected to the set input of flip-flop 241. Each CP-2 is appliedto the reset input of flip-flop 241, thereby maintaining the latternormally reset to 0. The clock pulse output from delay line 218 is alsoapplied to the input of a gate 240 which is armed by the 1 side outputterminal of flip-flop 241. The output of gate 240 is connected to thereset input of flip-flop 241 and to the set input of flip-flop 223. Eachinformation pulse representing a change from 0 to 1 of the band digit isoperated upon by triggers 231 and 232, flip-flop 241, and gates 233, 234and 240 in the manner hereinbefore described, and sets flipflop 223 to1; therefore, subsequent OPs from the output of gate 207 are transmittedthrough gate 225 and amplifier 227 to the ls Transfer Bus until the nextchange in the value of the band digit causes flip-flop 223 to be resetto 0.

In summary, the Interpreter identifies the proper time position of eachinformation pulse and thrn employs that pulse for controlling thetransmission of subsequent Os or ls pulses to the Memory Busses until aneXt information pulse is received. Briefly, the time position of eachinformation pulse is identified by detecting the amplitude of the pulseduring each digit interval embraced by the pulse. If the pulse has morethan a predetermined amplitude during a first digit interval, its timingis conditionally identified with the clock pulse occurring during thatdigit interval. If the information pulse is subsequently found to havemore than a second and higher predetermined amplitude during a seconddigit interval, the first identification is ignored, and the pulse isre-identified with the next clock pulse. If the information pulse doesnot have the higher minimum amplitude during the second digit interval,the first identification is retained. It will be seen that the aboveprinciple of multiple tampling of a signal can be extended to testingfor n minimum amplitudes during a corresponding n successive digitintervals, and ultimately identifying the timing of the informationpulse with the clock pulse occurring during the digitinterval in whichthe greatest amplitude is detected.

I claim.

1. In a computer having means for generating timing signals, a memoryunit with information signals stored therein in random distribution, andreading means co- Operating with said generating means and said memoryunit to sense the stored signals in timed relation to the generation ofsaid timing signals, the combination of: an output circuit; a normallyclosed output circuit gate having an input; means fortransmitting timingsignals from said generating means to the input of said gate; means forarming said gate, said arming means comprising; means connected to saidreading means and responsive to the reading of an information signal ofmore than a first predetermined amplitude to generate and energizingsignal; a conditioning circuit operable after a predetermined delayinterval following energization of said conditioning circuit for armingsaid gate; means including said energizing signal generating circuit forenergizing said conditioning circuit in response to the generation ofsaid energizing signal; means for testing the amplitude of saidinformation signal to detect the-occurrence of asecond predeterminedsignal amplitude greater than said first predetermined signal amptitude;means for de-energizing said conditioning circuit in response to thedetection of said second predetermined signal amplitude; and meansoperable in response to the detection of said second predeterminedsignal amplitude for re-energizing said de-energized conditioningcircuit after a time delay related to the time separation of twoconsecutive ones of said timing signals.

2. In a computer having means for generating timing signals, a memoryunit with information signals stored therein in random distribution, andreading means cooperating with said generating means and said memoryunit to sense the stored signals in timed relation to the generation ofsaid timing signals, the combination of: an output circuit; a normallyopen output circuit gate having an input;-means for transmitting timingsignals from said generating means to the input of said gate; andmeans-for disarming said gate, said disarming means comprising:disarming signal generating means connected to said reading means andresponsive to the reading of an information signal of more than a-firstpredetermined amplitude to generate a de-energizing signal; aconditioning circuit connected to said disarming signal generating meansfor disarming said gate after a predetermined delay interval followingenergization of said conditioning circuit; means connected to saidde-energizing signalgenerating means; for energizing saidconditioningcircuit in response to the generation of-said de-energizing signal;testing means connected to said reading means for testing the amplitudeof said information signal to detect the occurrence of secondpredetermined signal ampltiude greater than said first predeterminedsignal amplitude greater than said first predetermined signal amplitude;means connected to said testing means for de-energizing saidconditioning circuit in response to the detection of said secondpredetermined signal amplitude; and means operable in response todetection of said second predetermined signal ampltiude forre-energizing said conditioning circuit after a time delay related tothe time separation of two consecutive ones of said timing signals.

3. In a readout system for an information storage including a source oftiming signals and a source of aperiodic information signals, thecombination of: information signal amplitude measuring means; means forapplying said information signals to said signal measuring means in atimed relation to saidtiming signals; an out: put circuit having anenabled and a disabled state; means connected to said measuringmeansfonchanging thestate of said output circuit; in response to ,thedetection by said measuring meansof a first predetermined minimumamplitude of an information signal; and meansconnected to said measuringmeans for: delaying the changing of the output circuitstate for a timeinterval corresponding to the readout time of' a single character ofstored information, said delaying means being operable in response tothe subsequent detection by said measuring means of a secondpredetermined minimum amplitude of said information signal greater thansaid first amplitude.

4. In a readout system for an information storage including a source oftiming signals and a source of aperiodic information signals, thecombination of: means for measuring a first predetermined minimumamplitude of said information signals; means for measuring a secondpredetermined minimum amplitude of said information signals, said secondpredetermined minimum being of greater amplitude than said firstpredetermined minimum; means for applying said information signals tosaid measuring means in a timed relation to said timing signals wherebythe time interval between a predetermined number of timing signalscorresponds to the readout time of a single character of storedinformation; an output circuit having an enabled state and a disabledstate; output circuit gating means connected to said measuring means forchanging the state of said output circuit in response to the detectionby said first amplitude measuring means of said first amplitude of aninformation signal; and gate inhibiting means connected to saidmeasuring means for postponing the operation of said gating means forthe readout time of a single character of stored information only ifsaid second amplitude is detected during the information readoutinterval immediately succeeding that during which said first minimumsignal amplitude is detected.

5. In a circuit for synchronizing information signals with timingsignals, the combination of: a timing signal source; a time delaycircuit connected to said timing signal source; an information signalsource; an output cir cuit; an output gate having an input connected tosaid time delay circuit and an output connected to said output circuitfor passing a select one of said timing signals to correspond to eachinformation signal; a bistable device having an enabling state and adisabling state of operation; a connection to an arming terminal of saidoutput gate from an enabling output of said bistable device; a firstconditioning gate with an input connected to said time delay circuit andan output connected to an enabling input of said bistable device forcontrolling the passage of timing signals to said enabling input; afirst amplitude discriminator having an input connected to said sourceof information signals and an output connected to the arming terminal ofsaid first conditioning gate for arm: ing'said first conditioning gateto passthe timing signal occurring during each interval that aninformation signal is above a first predetermined amplitude; a secondconditioning gate with an input connected to said source of timingsignals and an output connected to a disabling input of said bistabledevice; and a second amplitude discriminator with an input connected tosaid source of in? formation signals and with an output connected to anarming terminal of said second conditioning gate for arming said secondgate to pass a timing signal to the disabling input of said bistabledevice, prior to conduction of said timing signal through said timedelay circuit, for triggering said bistable device to its disablingstate to thereby disable said output gate at the beginning of theinterval that an information signal is abovea sec 0nd predeterminedamplitude greater than said first predetermined amplitude.

6. In a system for synchronizing information signals with timingsignals, the combination of: an input circuit for receivingsaidinformation signals; an output circuit; timing signal gating means fortransmitting to said output circuit a select one ofsaid timing-signalsto correspond toeach of said information signals; and means for arm: ingsaid timing signal gating means during a third one of three timingsignal intervals to pass said select one of said timing signalscomprising: means connected tosaid input circuit for enabling saidtiming: signal gating means in response to an information signal havinga first voltage amplitude above a first predetermined amplitude duringsaid first timing signal interval, means connected to said input circuitfor disabling and then enabling said timing signal gating means inresponse to an information signal having a second voltage amplitudeabove a second predetermined amplitude greater than said first amplitudeduring a second timing signal interval, and means for transmitting saidselect timing signal to said output circuit through said enabled timingsignal gating means during a third timing signal interval.

7. In a circuit for supplying timed information signals according to arecorded fiux pattern on a magnetic medium, the combination of: a sourceof operating signals; a first transfer bus; a second transfer bus; 2.first output gate connected to said source of operating signals forpassing operating signals to said first transfer bus during theintervals that a flux pattern corresponding to a given representation isbeing read; a second output gate connected to said source of operatingsignals for passing operating signals to said second transfer bus duringthe intervals that a flux pattern corresponding to anotherrepresentation is being read; an output circuit bistable device having afirst and a second state of operation corresponding respectively to saidgiven representation and said other representation and with a firstoutput connected to an arming terminal of said first output gate andwith a second output connected to an arming terminal of said secondoutput gate for arming said gates according to the state of saidbistable circuit; a source of timing signals; a time delay circuitconnected to said source; a first control gate connected to said timedelay circuit for passing select ones of said timing signals to a firstinput of said bistable device for setting the device to said first stateof operation; a second control gate connected to said time delay circuitfor passing select ones of said timing signals to a second input of saidbistable device for setting the device to said second state ofoperation; a first bistable control device having first and secondinputs and with an output connected to an arming terminal of said firstcontrol gate; a second bistable control device having first and secondinputs and with an output connected to an arming terminal of said secondcontrol gate; a first conditioning gate with an input connected to theoutput of said time delay circuit and an output connected to said firstinput of said first bistable controldevice; a second conditioning gatewith an input connected to the output of said time delay circuit and anoutput connected to said first input of said second bistable controldevice; a reading transducer for transducing said flux patterns on saidmedium to respective negative and positive electric signalscorresponding respectively to said given representation and said otherrepresentation; a phase inverter coupled to said reading transducer forsupplying at a first phase inverter output a positive signalcorresponding to each negative signal from said transducer and forsupplying at a second phase inverter output a positive signalcorresponding to each positive signal from said transducer; a firstlower voltage amplitude discriminator with an input connected to saidfirst phase inverter output and with an output connected to the armingterminal of said first conditioning gate for arming said firstconditioning gate to pass the timing signals occurring during the periodthat a signal corresponding to said given representation is above afirst predetermined voltage amplitude; a second lower voltage amplitudediscriminator with an input connected to said second phase inverteroutput and with an output connected to the arming terminal of saidsecond conditioning gate for arming said second conditioning gate topass the timing signals occurring during the period that a signalcorresponding to said other representation is above a firstpredetermined voltage amplitude; a third conditioning gate having aninput connected to said timing signal source and an output connected tosaid second inputof said firstt bistable control device; a fourth cotrditioning gate having-an input connected to said timing signal sourceand an output connected to said second input of said second bistablecontrol device; a first upper voltage amplitude discriminator with aninput connected to said first phase inverter output and with an outputconnected to the arming terminal of said third conditioning gate forselectively arming said third conditioning gate to pass a timing signalto said second input of said first bistable control device prior toconduction of the timing signal through said time delay circuit for setting the first bistable control device to said second state of operationto thereby disable said first output control gate at the beginning of aninterval that a signal corresponding to said given representation isabove a second predetermined voltage amplitude greater than said firstpredetermined voltage amplitude; a second upper voltage amplitudediscriminator with an input connected to said first phase inverteroutput and with an output connected to the arming terminal of saidfourth conditioning gate for selectively arming said fourth conditioninggate to pass a timing signal to said second input of said secondbistable control device prior to conduction of the timing signal throughsaid time delay circuit for setting said second bistable control deviceto said second state of operation to thereby disable said second outputcontrol gate at the beginning of an interval that a signal correspondingto said other representation is above a second predetermined voltageamplitude greater than said first predetermined voltage amplitude.

8. In a circuit for supplying timed output signals according to arecorded flux pattern on a magnetic medium, the combination of: meansfor transducing said flux patterns to corresponding first and secondpolarity input signals; an input circuit for receiving said inputsignals; a source of operating signals; a source of timing signals; agated output circuit; a first output terminal corresponding to saidfirst polarity input signals; first control means for enabling saidgated output circuit to pass operating signals to said first outputterminal in response to a first polarity input signal, said firstcontrol means comprising first timing signal gating means, first controlmeans for arming and disarming said first timing signal gating means,means connected to said input circuit for setting said control means todisarm said gating means at the beginning of a first timing signalinterval to prevent passage of a first timing signal to said gatedoutput circuit in response to a signal amplitude of said input signalabove a first predetermined level, means connected to said input circuitfor setting said control means to arm said gating means after a timedelay from the beginning of said first timing signal interval inresponse to a signal amplitude of said input signal above a secondpredetermined level less than said first level, and means fortransmitting a timing signal to said output circuit through said enabledtiming signal gating means during a second timing signal interval to setsaid gated output circuit to pass operating signals to the outputterminal corresponding to the first polarity input signal; a secondoutput terminal corresponding to said second polarity input signals; andsecond control means for enabling said gated output circuit to passoperating signals to said second output terminal in response to a secondpolarity input signal, said second control means comprising a secondtiming signal gating means, second control means for arming anddisarming said second gating means, means connected to said inputcircuit for setting said control means to disarm said second gatingmeans at the beginning of a first timing signal interval to preventpassage of a first timing signal to said gated output circuit inresponse to a signal amplitude of said second input signal above a firstpredetermined level, means connected to said input circuit for settingsaid second control means to arm said second gating means after a timedelay from the beginning of said first timnew ine si nal int rval in r pn e signa mp itude o said; input- Signal above a second pnedeter mined,level less: than said first level, and means for ti ansmitting a timingsignal to said output circuit through said enabled timing signal gatingmeans during a second timing signal interval to set said gated outputcircuit to pass-operating signals to the output terminal correspondingto the second polarity input signal.

Refierencesflited in the file oftl'lis patent UNHTED STATES PATENTSJohnstone Jan, 211, 1 958

